displayport receiver doc id 15885 page 1 of 7 stdp4020, STDP4010 rev 3 data brief features ? enhanced displayport? (dp) receiver ? dp 1.1a compliant ? embedded displayport (edp) compliant ? 1, 2, or 4 lanes ? higher bandwidth ?turbo mode? (3.24 gbps per lane), supports: ? 1920 x 1080 (fhd) 120 hz/10-bit color video standard timings and 7.1 ch audio ? 2560 x 1600 (wqxga), 2560 x 2048 (qsxga) 60 hz/10-bit color graphics and 7.1 ch audio ? interface compatibilit y with wide range of display controller ics ? lvttl (60 wide) and lvds (quad bus) video interface ? 8-ch i2s and spdif audio interface ? robust aux channel ? link service, maintenance ? i2c-over-aux (mccs, ddc) ? ir, full duplex uart protocol ? configurable through i2c host interface ? supports hdcp 1.3 with on-chip keys ? hdcp repeater capability ? acts as upstream receiver ? aux to i2c bridge for edid, mccs pass through ? spread spectrum on displayport, lvds, and ttl interfaces for emi reduction ? supports deep color and color format conversion ? rgb/yuv (4:4:4) ? 10-bit color ? yuv (4:2:2/4:2:0 ) ? 12-bit color ? rgb (4:4:4) to yuv (4:4:4) conversion and vice-versa ? supports hbr/?turbo? speed over hbr/rbr- rated long cables (15 m and more) ? package ? 164 lfbga (12 x 12 mm / 0.8 mm) ? power supply voltages ? 3.3 v i/o; 1.2 v core applications ? digital tv, lcd monito r, mobile display, projector, etc q-lvds/ ttl video i2s/spdif audio dp input i2s/spdif transmitter crystal oscillator (optional) gpio i2c master i2c host interface bus formatter lvds/ttl outputs displayport receiver
stdp4020, STDP4010 doc id 15885 page 2 of 7 1. description the stdp4020 is a displayport receiver ic for the reception of secure, high-bandwidth uncompressed digital audio-video signals targeted for applications su ch as dtv, lcd monitor, projector, and other types of display systems. stdp4020 is a vesa dp 1.1a and edp co mpliant device, impl ementing a single link displayport input port comprising four main lanes, auxiliary channe l, and hpd. in addition to the standard hbr (2.7 gbps) and rbr (1.62 gbps) speeds, this device supports turbo speed of 3.24 gbps per lane with a total link bandwidth of 12.96 gbps. the higher bandwidth provides unique benefits to users over other commercial dp receivers for embedde d applications by offering additional margin to support higher color depth, resolution, and refres h rate. for example, stdp4020 supports fhd non- reduced blanking video (1080p 30-bit color per pixe l) at 120 hz, plus 7.1 ch audio for two-box tv applications.the advanced equalizer built in this devi ce offers guaranteed performance over long reach cables. the auxiliary channel in stdp4020 acts as a bidirectional communication lin k, supporting application-specific protocols such as mccs, ddc, uart, ir, as well as the dedicated displayport link training and device management functions. the stdp4020 supports rgb and yuv video color format s with color depth of 12 (yuv 4:2:2 only), 10, and 8 bits. this device offers lvds and lvttl output interfaces configurable to map a wide range of display controller products. the quad lvds interfac e supports video signals up to 400 mhz pixel rate with flexible channel and lane swapping options. the 60-bit lvttl output ports can be mapped to transfer video data either in two pixels per clock or single pixel per clock up to 330 mhz pixel rate, which opens up possibilities for 3d ap plications. the stdp4020 also supports both compressed and uncompressed audio formats. the extracted audio signal is transferred on a digital audio output bus. this device comprises four i2s audio output, supporting up to 8 channel lpcm audio and a single wire s/pdif output for encoded audio. the stdp4020 feat ures the hdcp 1.3 content protection scheme with an embedded key option for secure reception of digita l audio-video content. in addition, it also supports the hdcp repeater function and, thus acts as an upstream receiver suitable for two-box tv and hdmi/dvi converter applications. the stdp4020 is configurable from an external host co ntroller through i2c host in terface. this ic also includes general-purpose inputs/outputs for controlling system components. the st dp4020 features a color space converter (rgb to yuv and yuv to rg b) for flexible interface with external video processing devices.
stdp4020, STDP4010 doc id 15885 page 3 of 7 2. application overview the stdp4020 is designed as a displayport front-end capture device for display applications. typical display design has a display contro ller (scaler) that acts as system master (host). the host controller configures stdp4020 through a 2-wire host interface. the host and stdp4020 also use interrupt mechanism whenever the slave needs attention. th e stdp4020 may require an external spi flash to store firmware for supporting custom specific app lications. the audio and video output from stdp4020 can directly interface to the host display controller for further processing. the aux i2c bypass channel handles the i2c traffic between stdp4020 and host controller, as shown in the figure below. figure 1. system interface block diagram stdp4020 dp connector main link aux ch video controller / host controller ttl / lvds i 2 c master host i 2 c dp edid spi flash intr i 2 c slave ddc input aux i 2 c hpd_out spdif/i2s video audio display audio amp speakers spi l/r audio dp / lvds
stdp4020, STDP4010 doc id 15885 page 4 of 7 3. feature attributes ? enhanced displayport (dp) receiver compliant with dp1.1a and embedded (edp) specification ? supports higher bandwidth mode called ?turbo mode? (3.24 gbps per lane) for embedded applications. for example, supports fhd 120 hz -10/12-bit video or qsxga (2560 x 2048) 60 hz/10-bit color graphics and 7.1 ch audio ? interface compatibility wit h wide range of display products. supports lvttl (60 wide) and quad lvds video interface ? supports i2s 8 ch and spdif audio output in terface compliant with iec60958 and iec61937 audio formats. ? robust aux channel for link service, mainten ance and supports i2c over aux, mccs, ddc, ir and full duplex uart protocol ? supports hdcp 1.3 with on-chip key storage ? acts hdcp repeater for an upstream receiver ? supports aux to i2c bridge for edid, mccs pass through ? spread spectrum on displayport, lvds and ttl interfaces for emi reduction ? supports deep color and color format conversion: rgb (4:4:4) to yuv (4:4:4) and vice-versa ? supports ttl up to 330 mhz pixel clock, which allows 3d video applications ? supports hbr/?turbo? speed over hbr/rbr rated long cables (15 m and more) ? configurable through i2c host interface ? package: 164 lfbga (12 x 12 mm / 0.8 mm) ? power supply voltages: 3.3 v i/o; 1.2 v core
stdp4020, STDP4010 doc id 15885 page 5 of 7 4. ordering information table 1. order codes part number description stdp4020-ad 164 lfbga (12 x 12 mm) STDP4010-ad 164 lfbga (12 x 12 mm)
stdp4020, STDP4010 doc id 15885 page 6 of 7 5. revision history table 2. document revision history date revision changes 10-sep-2009 1 initial release. 28-may-2014 2 updated to comply with mega chips documentation style/formatting. 15-sep-2014 3 updated footers and added copyright information to last page.
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